1 SED1640 wide voltage operation products ssc5000series dot matrix high duty lcd driver pf669-03 SED1640 1 description the SED1640 is the 80-segment (column) output driver that is appropriate to driving of a large-capacity, dot-matrix lcd panel. the chip has been designed to improve the lcd display quality and it provides the high-speed enable chain method useful for lower power operation. the flat chip design allows more compact lcd panel production. the logic power supply allows low-voltage operation in a wide range of applications. features no. of lcd drive outputs ................................. 80 super slim chip design low current consumption low voltage operation ..................................... ?.7 vdc max. wide range of lcd drive ................................. ? to ?8 vdc voltages high-speed data transmission at the low ........ shift clock frequencies : 6.5 mhz (at ?.7 vdc) power by 4-bit bus enable chain method : 7.5 mhz (at ?.0 vdc) non-bias display off function available pin selection in output shift direction available offset bias adjustment of lcd power supply for v dd level logic power supply ......................................... ?.7 to ?.5 vdc package .......................................................... die form (au bump): SED1640d 0b block diagram v 0 v 5 fr dspoff lp v ss v dd d0 - d3 xscl eio1 v 2 v 3 shl eio2 o0 o79 80-bit lcd driver 80-bit level shifter 80-bit latch 80-bit data register enable shift register 80-bit output 1/300 duty max. 2.7 to 5.5vdc logic power supply
2 SED1640 pin description absolute maximum rating rating symbol value unit power voltage (1) v ss 7.0 to +0.3 v power voltage (2) v 5 30.0 to +0.3 v power voltage (3) v 0 , v 2 , v 3 v 5 0.3 to v dd +0.3 v input voltage v i v ss 0.3 to v dd +0.3 v output voltage v o v ss 0.3 to v dd +0.3 v eio output current i01 20 ma operating temperature topr 40 to +85 ? c storage temperature 1 tstg 1 65 to +150 ? c storage temperature 2 tstg 2 55 to +100 ? c notes: 1. all voltages are based on v dd = 0 v. 2. storage temperature 1 defines the storage temperature of the separate chip, and storage temperature 2 defines the tab mounted chip. 3. the v 0 , v 2 and v 3 voltages must always satisfy the following: v dd v 0 c2 c3 v 5 4. if the logic power supply is floating or if it exceeds v ss = 2.6 vdc when the lcd drive is powered, the lsi may be destroyed permanently. cares must be taken especially when the system power supply is turned on or off. terminal name i/o function no. of pins o0 to o79 o lcd drive segment output; the output changes at the lp falling edge. 80 d0 to d3 i display data input 4 xscl i shift clock input of display data (falling edge trigger) 1 lp i latch pulse input of display data (falling edge trigger) 1 eio1 i/o enable i/o 2 eio2 the terminals are set to the input or output according to the shl input signal level. the output is reset by lp input. when the 80-bit data is read, the signal automatically goes high. shl i used for shift direction selection and i/o control input of eio terminal. 1 if data sets (a, b, c, d) (e, f, g, h) ... (w, x, y, z) are entered in this sequence in terminals (d3, d2, d1, d0), the data and segment output are processed as follows: note: the relationship between the data and segment output is determined regardless of the number of shift clocks. fr i ac conversion signal input of lcd drive output 1 v dd , v ss power supply logic power supply v dd : 0 v v ss : 2.7 to 5.5 vdc 3 v 0 , v 2 , v 3 power supply power supply for lcd drive circuit v dd : 0 v v 5 : 8 to 28 vdc 8 v 5 v dd v 0 v 2 6/9 v 5 *1 3/9 v 5 v 3 v 5 i forced blank input 1 dspoff when the signal level is low, the output is forcibly set to v0 level. note: if this function is used, the sed1631 cannot be used as a pair. *1 a pair of v0 to v 5 must always be connected to their dedicated lcd power supplies. total: 107 (nc: 5) s output eio h l 79 78 77 2 1 0 eio1 eio2 la b c x y z output input hz y x c b a input output > = > = > = > = > = 5v v ss v dd v 0 v 2 v 3 v 5 28v > = > = > = > =
3 SED1640 electrical characteristics dc chracteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - < = < = (v dd = v0 = 0 v, v ss = -5.0 vdc 10%, ta = -40 to +85 ? c unless otherwise specified.) characteristic symbol condition pin applied min. typ. max. unit power voltage (1) v ss v ss -5.5 -5.0 -2.7 v recommended v 5 v ss = -2.7 to -5.5 vdc v 5 -28.0 -12.0 v operating voltage operable voltage v 5 function v 5 -8.0 v power voltage (2) v 0 recommended value v 0 v dd -2.5 v dd v power voltage (3) v 2 recommended value v 2 3/9v 5 v power voltage (4) v 3 recommended value v 3 v 5 6/9v 5 v high-level input voltage v ih eio1, eio2, fr 0.2v ss v v ss = -2.7 to -5.5 vdc d0 to d3, xscl low-level input voltage v il shl, lp, dspoff 0.8v ss v high-level output voltage v oh v ss =i oh = -0.6 ma v dd -0.4 v -2.7 to eio1, eio2 low-level output voltage v ol -5.5 vdc i ol = 0.6 ma v ss +0.4 v input leakage current ili v ss v in v dd d0 to d3, lp, fr, 2.0 a xscl, shl, dspoff i/o leakage current ili/o v ss v in v dd eio1, eio2 5.0 a static current i ss v 5 = -28.0 to -14.0 vdc v ss 25 a v ih = v dd , v il = v ss output resistance v on = 0.5v o 0 to o 79 1.5 2.5 k ? r seg v 5 = -20.0 v, v 3 =13/15 v 5 v 2 = 2/15 v 5 , v 0 =v dd average operating v ss = -5.5 vdc, v ih = v dd , current consumption (1) v il = v ss , f xscl = 2.69 mhz, 0.10 0.2 ma f lp = 16.8 khz, f fr = 70 hz, i ss input data: stripe display, no load v ss v ss = -3.0 vdc ; 0.07 0.15 others are the same as v ss = -5 vdc. average operating v ss = 5.0 vdc, v 0 = 0.0 v, current consumption (2) i 5 v 2 = 9.3 vdc, v 3 = 18.6 vdc, v 5 0.02 0.05 ma v 5 = 28.0 vdc; others are the same as i ss . input terminal capacity c i d0 to d3, lp, fr, freq. = 1 mhz, xscl, shl, dspoff 8pf ta = 25 ? c, i/o terminal capacity c i/o separate chip eio1, eio2 15 pf
4 SED1640 ac characteristics input timing characteristics t wlh t df t lh t ld t ds t dh t wch t wcl t c t sue fr lp xscl d0 ~ d3 eio1, 2 ( in ) (v ss = 5.0 v 0.5, ta = 40 to 85 ? c) characteristic symbol condition min. max. unit xscl cycle t c 100 ns xscl high-level pulse width t wch 30 ns xscl low-level pulse width t wcl 30 ns data setup time t ds 30 ns data hold time t dh 20 ns xscl-to-lp rise time t ld 0ns lp-to-xscl fall time t lh 40 ns lp high-level pulse width t wlh *3 40 ns fr delay allowance time t df 900 +900 ns eio setup time t sue 35 ns (v ss = 4.5 v to 2.7 v, ta = 40 to 85 ? c) characteristic symbol condition min. max. unit xscl cycle t c v ss = 2.7 v *1 153 ns v ss = 3.0 v *2 133 xscl high-level pulse width t wch 50 ns xscl low-level pulse width t wcl 50 ns data setup time t ds 50 ns data hold time t dh 30 ns xscl-to-lp rise time t ld 0ns lp-to-xscl fall time t lh v ss = 2.7 v 75 ns v ss = 3.0 v 65 lp high-level pulse width t wlh v ss = 2.7 v *3 75 ns v ss = 3.0 v *3 65 fr delay allowance time t df 900 +900 ns eio setup time t sue v ss = 2.7 v 50 ns v ss = 3.0 v 40 *1 equivalent to 6.5 mhz *2 equivalent to 7.5 mhz *3 t wlh defines the time when lp is high and xscl is low.
5 SED1640 ac characteristics output timing characteristics fr lp xscl seg eio1, 2 (out) t frsd t lsd t er t dcl 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 1 100 105 (0, 0) chip size: 11.59 1.40 mm pad pitch: 105 m (min.) chip thickness: 625 m 25 m (1) SED1640d ob au bump specifications (reference) bump size a : 106 m 80 m 4 m (pad nos. 2 to 26) bump size b : 86 m 91 m 4 m (pad nos. 1, 27, 37, 98) bump size c : 86 m 68 m 4 m (pad nos. 28 to 36, 99 to 107) bump size d : 82 m 74 m 4 m (pad nos. 38 to 97) bump height a to d : 22.5 5.5 m (pad nos. 1 to 107) pad layout (v dd = 5.0 0.5 v, v5 = 12.0 to 28.0 v) characteristic symbol condition min. max. unit eio reset time t er 90 ns c l = 15 pf (eio) eio output delay time t dcl 55 ns delay time from lp to segment output t lsd c l = 100 pf 200 ns delay time from fr to segment output t frsd (0 .... n) 400 ns (v dd = 4.5 to 2.7v, v5 = 12.0 to 28.0 v) characteristic symbol condition min. max. unit eio reset time t er 150 ns c l = eio output delay time t dcl 15 pf v ss = 2.7 v 95 ns (eio) v ss = 2.7 v 85 delay time from lp to segment output t lsd c l = 100 pf 400 ns delay time from fr to segment output t frsd (0 .... n) 800 ns
6 SED1640 pad coordination pad no. pad name x coordinate y coordinate 2v 0 5345 541 3v 2 5164 4v 3 4984 5v 5 4594 6v ss 4091 7 dummy 3839 8 shl 3587 9 dummy 3065 10 dummy 2828 11 v dd 2590 12 dspoff 2086 13 fr 1583 14 lp 1079 15 xscl 1079 16 d0 1583 17 d1 2086 18 d2 2590 19 dummy 3065 20 d3 3587 21 dummy 3839 22 v ss 4091 23 v 5 4594 24 v 3 4984 25 v 2 5164 26 v 0 5345 27 eio1 5644 544 28 o0 426 29 o1 320 30 o2 215 31 o3 109 32 o4 4 33 o5 102 34 o6 207 35 o7 313 36 o8 418 37 o9 546 pad no. pad name x coordinate y coordinate 38 o10 5269 553 39 o11 5090 40 o12 4912 41 o13 4733 42 o14 4554 43 o15 4376 44 o16 4197 45 o17 4019 46 o18 3840 47 o19 3661 48 o20 3483 49 o21 3304 50 o22 3126 51 o23 2947 52 o24 2768 53 o25 2590 54 o26 2411 55 o27 2233 56 o28 2054 57 o29 1875 58 o30 1697 59 o31 1518 60 o32 1340 61 o33 1161 62 o34 982 63 o35 804 64 o36 625 65 o37 447 66 o38 268 67 o39 89 68 o40 89 69 o41 268 70 o42 447 71 o43 625 72 o44 804 73 o45 982 pad no. pad name x coordinate y coordinate 74 o46 1161 553 75 o47 1340 76 o48 1518 77 o49 1697 78 o50 1875 79 o51 2054 80 o52 2233 81 o53 2411 82 o54 2590 83 o55 2768 84 o56 2947 85 o57 3126 86 o58 3304 87 o59 3483 88 o60 3661 89 o61 3840 90 o62 4019 91 o63 4197 92 o64 4376 93 o65 4554 94 o66 4733 95 o67 4912 96 o68 5090 97 o69 5269 98 o70 5644 546 99 o71 418 100 o72 313 101 o73 207 102 o74 102 103 o75 4 104 o76 109 105 o77 215 106 o78 320 107 o79 426 1 eio2 544
7 SED1640 electronic devices marketing division notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arisi ng out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no re presentation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material wil l be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject rela ting to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2000 all right reserved. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. first issue august, 1995 printed in february, 2000 japan h ic marketing & engineering group ed international marketing department i (europe, u.s.a) 421-8 hino, hino-shi, tokyo 191-8501, japan phone: 042 587 5812 fax: 042 587 5564 ed international marketing department ii (asia) 421-8 hino, hino-shi, tokyo 191-8501, japan phone: 042 587 5814 fax: 042 587 5110 http://www.epson.co.jp/device/ electronic devices information on the epson www server.
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